Trend of High-Speed SAR ADC towards RF Sampling

One emerging trend of high-speed low-power ADC design is to leverage the successive approximation (SAR) topology. It has successfully advanced the power efficiency by orders of magnitude over the past decade. Given the nature of SAR algorithm, the conversion speed is intrinsically slow compared to other high-speed ADC architectures, and yet minimal static power is required due to the mostly digital implementation. This paper examines various speed enhancement techniques that enable SAR ADCs towards RF sampling, i.e. >GS/s sampling rate with >GHz input bandwidth, while maintaining low power and area consumption. It is expected to play a crucial role in the future energy-constrained wideband system.